1. Field of the Invention
The invention relates to delta sigma modulators, and more particularly to compensation for loop delay of delta sigma modulators.
2. Description of the Related Art
Delta sigma modulators can be used to execute analog-to-digital conversion or digital-to-analog conversion. Conventional delta sigma modulators are discrete-time delta sigma modulators. Discrete-time delta sigma modulators can provide output signals with high resolutions and low bandwidths. To provide output signals with higher bandwidths and higher resolutions, continuous-time delta sigma modulators have been introduced. Continuous-time delta-sigma modulators, however, may generate unstable output signals due to signal delay in feedback loops. Thus, a method for compensating continuous-time delta-sigma modulators for loop delay is required so as to provide continuous-time delta-sigma modulators with high stability.
Referring to FIG. 1A, a block diagram of a conventional second-order continuous-time delta sigma modulator 100 is shown. The second-order delta sigma modulator 100 comprises two integrators 104 and 108, two summation stages 102 and 106, two digital-to-analog converters 112 and 114, and a quantizer 110. Because the delta sigma modulator 100 is a second delta-sigma modulator, it comprises two integrators 104 and 108 connected in series. The integrators 104 and 108 generate an analog output signal Vop according to an analog input signal Vin. The quantizer 110 quantizes the analog input signal Vin to generate a digital output signal Dout as the output of the delta-sigma modulator 100. The digital output signal Dout is then converted from digital to analog by digital-to-analog converters 112 and 114, and fed back and respectively subtracted from input signals of the integrators 104 and 106 by summing stages 102 and 106.
Referring to FIG. 1B, a physical circuit 150 of the second-order continuous-time delta sigma modulator 100 is shown. The integrators 104, 108 and the summation stages 102, 106 of delta sigma modulator 100 are physically formed with a circuit 170 comprising two operational amplifiers 172 and 174. The quantizer 160 and digital-to-analog converters 162, 164 of the circuit 150 respectively correspond to the quantizer 110 and digital-to-analog converters 112, 114 of the delta sigma modulator 100.
The feedback loop feeding the digital output signal Dout back to the summing stages 102 and 106, but however often delays the digital output signal Dout for a delay period of a few hundreds of a nanoseconds, referred to as loop delay. The excess loop delay is denoted by a delay time τ in the feedback loop of FIG. 1B. The loop delay negatively affects the stability of the system. Modules in the feedback loop, such as the quantizer 110 and the digital-to-analog converters 112 and 114, may delay the digital output signal Dout in the feedback loop. If the loop delay exceeds a threshold of about 800 nanoseconds, the delta sigma modulator 100 becomes an unstable system, and signal-to-noise ratio of output signal Dout will be greatly reduced.
To compensate for the loop delay in the feedback path, an extra feedback path is added to compensate the input signal of the quantizer. Referring to FIG. 2A, a block diagram of a delta sigma modulator 200 with a compensation feedback path 230 compensating for a loop delay is shown. The compensation feedback path 230 comprises a digital-to-analog converter 232 and a summation stage 234. The digital-to-analog converter 232 converts the digital output signal Dout from digital to analog to obtain a feedback signal VF. The summation stage 234 then subtracts the feedback signal VF from the analog output signal Vop generated by the integrator 208 to obtain a compensated signal Vop′ as the input of the quantizer 210. Because the input signal Vop′ of the quantizer 210 is compensated for the loop delay, the output signal Dout of the quantizer 210 is stabilized and has a higher signal-to-noise ratio.
The rationale for adding the compensation feedback path 230 is illustrated in the following. Suppose the delta-sigma modulator 100 without loop delay has a noise transfer function of n(z)/d(z). If a delay module 180 causing the loop delay is added to the delta-sigma modulator 100 to obtain the delta-sigma modulator 150, the noise transfer function of the delta-sigma modulator 150 is then determined by the following algorithm:
            NTF      ⁡              (                  z          ,                      τ            d                          )              =                            n          ⁡                      (            z            )                                    d          ⁡                      (            z            )                              +                        z                      -            1                          ⁢                                                            A                ⁡                                  (                                      τ                    d                                    )                                            ⁢                              z                2                                      +                                          B                ⁡                                  (                                      τ                    d                                    )                                            ⁢              z                        +                          C              ⁡                              (                                  τ                  d                                )                                                          d            ⁡                          (              z              )                                            ;
wherein τd is the loop delay. The high order terms [A(τd)z2+B(τd)z+C(τd)] causes the system to be unstable. If a compensation feedback path 230 is added to the delta-sigma modulator 150 to obtain the delta sigma modulator 200, the delta-sigma modulator 200 is then determined by the following algorithm:
            NTF      ⁡              (                  z          ,                      τ            d                          )              =                            n          ⁡                      (            z            )                                    d          ⁡                      (            z            )                              +                        z                      -            1                          ⁢                                                            A                ⁡                                  (                                      τ                    d                                    )                                            ⁢                              z                2                                      +                                          B                ⁡                                  (                                      τ                    d                                    )                                            ⁢              z                        +                          C              ⁡                              (                                  τ                  d                                )                                                          d            ⁡                          (              z              )                                          +                        z                      -            1                          ⁢                                            -                              a                f                                      ⁢                          d              ⁡                              (                z                )                                      ⁢                          z                              -                1                                                          d            ⁡                          (              z              )                                            ;
wherein the af is the gain of the feedback loop. Thus, the new term [−af×d(z)×z−1] due to the compensation feedback path 230 cancels off the high order terms [A(τd)z2+B(τd)z+C(τd)] to compensate for the loop delay effect.
Although the feedback path 230 compensates the delta-sigma modulator 200 for loop delay, the feedback path 230 requires expensive hardware cost. Referring to FIG. 2B, a physical circuit 250 of the delta sigma modulator 200 of FIG. 2 is shown. The compensation feedback path 230 is implemented with a circuit 280 comprising a digital-to-analog converter 282 and an operational amplifier 284. The operational amplifier 284 is a complex circuit and requires great amount of currents to operate, complicating the circuit design of the delta-sigma modulator 200 and increasing power consumption. Thus, a method for compensating a continuous-time delta-sigma modulator for loop delay with low circuit complexity and low power consumption is required.